This modification turns the Ultimate3 kit into an accurate GPS-disciplined frequency reference (approx 0.03Hz accuracy). The firmware has NOT yet been updated to operate with the Si5351A synthesiser module therefore this modifcation cannot be done with the U3S kit.
The input frequency to the ATmega series of Atmel AVR microcontrollers limited to 40% of the system frequency. With the U3's 20MHz system frequency, this means the upper limit for direct counting is 8MHz. If you want to turn a U3 into a frequency reference with no more than 8MHz output, then all you need is a special firmware version. If you want to generate an output reference frequency higher than 8MHz then you will need to make a hardware modification as described below.
This modification requires a special, beta (maybe we should even say Alpha), firmware chip. You can program your own ATmega328 if you wish, using the files in the QRP Labs YahooGroups forum. Or we can provide a programmed ATmega328 chip, on request (this beta firmware chip is not available from shop).
On power up you will see the following screen:
The v00003.08 is nothing at all related to the normal Ultimate3 firmware versions, it is simply a Beta firmware ID. Please think nothing more about that.
The set up of the parameters is done in the same way as the U3, but the set of parameters is greatly simplified. There are only three parameters, as follows.
"Frequency" sets the output frequency, your desired GPS-disciplined frequency reference. It can be anywhere in the DDS's available output range, 0 - 40MHz. But if you want an output frequency higher than 8MHz, then you will need to make a hardware modification as described in the section lower down this page.
"Divider" sets the external division ratio. If you are using an output frequency of not more than 8MHz in an un-modified U3, then you leave this at its default value of 1. If however, you are using an external divider chip as described in the hardware modification section below, then you must set this parameter to whatever the external division ratio is. More on this later.
This Reference Frequency is just the same as in the U3 kit, it is the frequency of the DDS reference oscillator. If you wished to, you could not use a GPS, and set this frequency to a measured (or calculated) value. Of course you wouldn't have temperature drift compensation, in this case.
Method of GPS discipline action
The firmware applies a continual correction, measuring the output frequency once every second using the GPS 1pps signal as the counter gate. This is unlike the U3, where the frequency correction only occurs in the calibration period that takes place in between transmission cycles. The firmware applies two methods for the frequency correction. An initial "Coarse" method to get the frequency locked on target, then a "Fine" method to keep it there during gentle temperature-induced frequency drift.
The "Course" method measures the DDS output frequency and compares it to the set target output frequency (that you entered in the Frequency parameter). The error is added or subtracted to the Ref. Frq. setting and the DDS tuning word is recalculated. Imagine for simplicity that your desired reference frequency is 1/20th the 125MHz DDS reference oscillator, i.e. 6.25MHz. A measured error of 10Hz is added to the 125MHz setting, and the DDS word re-calculated for the next second. Of course this correction is only 1/20th of what would really be required to compensate for the 10Hz error, due to the dividing action of the DDS. This means even the coarse mode correction is quite gentle.
(Note that the system does not currently write anything back to the EEPROM. Next time you power up, or next time you cycle through the menu, everything starts again from the beginning).
Eventually the measured error (between actual measured frequency and target frequency) becomes zero, and at this point the system switches over to the "Fine" method.
The "Fine" method stops adjusting the Ref Frq and re-calculating the DDS tuning word. Instead, it directly increases or decreases the DDS tuning word itself, by an amount equal to the measured error. Now this is very fine because if the measured error is 2Hz, then the applied correction will be 2 * the DDS tuning resolution of 0.029Hz, which means only 0.058Hz. In the practical case the actual error will be 1Hz or 0Hz, assuming there are no sudden temperature changes. The system therefore will keep adjusting the DDS tuning word, at every 1 second, by 0.029Hz in one direction or the other. A measured frequency of greater or equal than the target results in a down-step, a measured frequency less than the target results in an up-step. This 0.029Hz minimum DDS step is the accuracy of the GPS-disciplined frequency reference: +/- 0.03Hz (roughly speaking).
Note that if you are using external hardware division, for an output frequency of more than 8MHz, then the error measurement is on the divided value. For example, if you have chosen to have an output frequency of 10.000000MHz, and an external division ratio of 2, then the frequency that hits the processor is 5MHz, and the error measurement will be against a target value of 5MHz also.
Hardware modification for more than 8MHz output
This hardware modification, as I mentioned, is only required if you want to use an output frequency of more than 8MHz, because 8MHz is the maximum frequency that these AVR microcontrollers can count. You therefore must arrange for division to occur, between the DDS output and the AVR frequency counter input, to ensure that the 8MHz limit is not broken. For example: if using a disciplined output frequency of 10MHz, you could use a divide-by-2 chip, resulting in 5MHz to the AVR. If using an output frequency of 20MHz, then you could divide by 3. However generally powers of 2 are more practical, so a division ratio of 4 would be easier.
The AVR frequency counter input is at pin 11 in the U3. You need to cut the trace at this pin and wire in the external divider. Turn over the U3 PCB and look at the underside (NOT the component side). You can find the track at pin 11, circled in RED in the image below. This shows a Revision 4 PCB but the same applies to any of the PCB revisions. Check you have the right pin! On the chip itself, there is a little dimple next to pin 1 of the chip. Count down the left side of the chip to pin 11. My recommendation is to cut the track very carefully as close to the pin as possible. Be careful not to damage any nearby track or connection. Then you can wire the external divider in. I don't know where you want to physically put the divider chip, this is for you to work out, but it's always a good idea to keep wire lengths as short as possible. If you're careful you could fit the chip and a small piece of board, between the LCD module and the main PCB.
A number of IC's are suitable as dividers. You could use a 74HC74 (dual D-type flip flop). My personal favourite is the 74HC393, because it contains two 4-bit binary dividers so you can use it for division ratios up to 256, in a single chip. Not that we'll ever need 256 in this application. Come to think of it, the 74HC4040 is even nicer as it is a single 12 bit counter, that gives a division ratio up to 4,096.
Alright, so you need to work out how to connect your chosen divider. As an example let's assume you use a 74HC393 as I did. And you want a division ratio of 2, for use with a 10MHz output frequency. You will set the "Frequency" parameter to 10,000,000 and the "Divider" parameter to "02". On the hardware side, you need to make the following connections:
Pin 1: the divider input. Connect it to the squarewave frequency output on one side of the cut track, that is connected to pin 7 of the DDS, and also connected to the gates of the three PA transistors Q2, Q3 and Q4.
Pin 2: the counter clear input. We don't need it, so connect it to Ground.
Pin 3: this is the divide-by-2 output: connect it to the AVR pin 11, on the other side of the cut track. If you need a divide-by-4 ouput, use pin 4 instead; for divide-by-8, use pin 5, etc.
Pin 7: connect to Ground (it is a voltage supply pin of the 74HC393).
Pins 12 and 13 are Clear and Clock input to the other side of the divider. We don't need them here, as we aren't trying to divide by 16 or more. But we shouldn't really leave them floating, so connect them both to Ground, to be on the safe side.
Pin 14: connect to +5V (it is a voltage supply pin of the 74HC393). Also, it is good practice to connect a decoupling capacitor of between 0.01 and 0.1uF between pin 7 and pin 14, as close as possible to the chip.
Any suggestions to improve the firmware, please email them. The firmware files are available in the QRP Labs YahooGroups forum. If you want an actual chip these are available on request (not listed in the QRP Labs shop).